1. Field of the Invention
This invention relates to a semiconductor device, and, in particular, to a selectively definable semiconductor device whose function and/or structure may be selectively defined, as desired. More specifically, the present invention relates to a composite gate-array semiconductor device including both a general purpose cell region only for a logic function and a dedicated cell regions for a particular function, each region being capable of serving as an interconnection region.
2. Description of the Prior Art
A gate-array semiconductor device is an integrated logic circuit, wherein a masterslice chip having a predetermined array of cells is fabricated in advance and then a desired interconnection is formed on the masterslice chip to define a desired functional circuit. Such a gate-array semiconductor device is particulary suited for manufacturing semiconductor integrated circuit devices small in number but large in variety in a short period of time and low at cost.
In order to increase the level of integration, there is proposed a gate array semiconductor device having an exclusive region for a read only memory (ROM) or random access memory (RAM). Such a gate array device including an exclusive memory region has advantages of excellent memory characteristic, such as short access time, and of increased density; however, the effective integration level becomes rather lowered if the memory capacity required by the user is smaller than the memory capacity of the exclusive memory region provided in the masterslice.
As disclosed in Japanese Patent Laid-open Pub. No. 59-11670, there is also proposed a semiconductor integrated circuit device provided with two kinds of first general purpose cells exclusive use for logic functions and second general purpose cells exclusive use for memory, wherein the first general purpose cells are used for interconnections where a large memory capacity is required and the second general purpose cells are used for interconnections where a large capacity for logic functions is required so as to optimize the rate of cell use irrespective of the required ratio between memory elements and logic elements. However, with such an approach, although there is a flexibility for the memory capacity and for placement in the gate-array chip, the level of integration is not so high and the memory characteristic is not so good.